The present invention relates to a wide band I (Inphase) and Q (Quadrature) splitting apparatus, especially, to a wide band IQ splitting apparatus suitable for application in frequency domain analysis, and to a calibration method for the wide band IQ splitting apparatus.
A spectrum analyzer is used for analyzing the frequency domain of a signal under test. The spectrum analyzer often has an IQ splitter for getting the frequency domain data. There are two types of IQ splitters, i.e., digital and analog types.
FIG. 1 shows a block diagram of a conventional digital IQ splitter. A frequency converter (not shown) which has a mixer and a local oscillator etc. converts an input signal under test to an intermediate frequency (IF) signal. An analog to digital converter (ADC) 10 converts the analog IF signal into a digital signal. A digital IQ splitter 12 splits the digital signal from the ADC 10 into a digital I (In-phase) signal and a digital Q (Quadrature) signal. The I and Q signals are the components of the IF signal having a phase difference of 90 degrees. A digital signal processor (DSP) 14 transforms the digital I and Q signals into the frequency domain data by the FFT (Fast Fourier Transform) process. A memory 16 stores the data from the DSP 14, which are used to display the signal analysis result in the frequency domain on a suitable display (not shown), such as a CRT or a liquid crystal display.
The conventional configuration described above is satisfactory for relatively narrow band signal analysis but causes some problems if it is used for a wider band signal analysis. The sampling theorem states that the sampling frequency in the analog to digital conversion must be at least twice the maximum frequency of the analog input signal. In the case of wider band analysis, the maximum frequency of the IF signal is higher than in the case of narrow band analysis so that the sampling theorem requires that the sampling frequency of the ADC should be higher. Besides, the frequency domain analysis generally requires higher dynamic range, such as 12 or more bits, than the time domain analysis does, such as 8 bits at most. This also makes it difficult to make the sampling frequency of the ADC higher in the frequency domain analysis. The higher sampling frequency of the ADC leads to a higher data transfer rate and a need for higher operation speeds of the following devices, such as the DSP and the memory. As described, the wider band signal analysis brings technical and economical problems.
One solution of the above problem is to use an analog IQ splitter as shown in FIG. 2. A quadrature oscillator 17 generates a pair of quadrature signals, or sine and cosine signals which have the same frequency and amplitude and a phase difference of 90xc2x0. An analog IQ splitter 18 mixes an analog IF signal with the quadrature signals to split the analog IF signal into analog I and Q signals. The I signal is Input(t)*cos(bt) and the Q signal is Input(t)*sin(bt) where Input(t) is the input signal. ADCs 11 and 13 convert the analog I and Q signals into the digital I and Q signals, respectively.
FIG. 3 shows a schematic block diagram of the analog IQ splitter. A quadrature mixer 21 mixes the pair of quadrature signals with the analog IF signal to produce the analog I and Q signals. The frequency of the quadrature signals from the quadrature oscillator 17 is the same as the center frequency of the band of the analog signal. For example, if the band of the analog IF signal is from 35 MHz to 65 MHz (the bandwidth is 30 MHz, the center frequency is 50 MHz), the frequency of the quadrature signals from the quadrature oscillator 17 is 50 MHz. The analog I and Q signals pass low pass filters (LPFs) 23 and 25 to have suitable bandwidths, respectively. In this operation, the bandwidths of the analog I and Q signals are reduced to approximately half, respectively. This is, for example, shown as the following equations:
Input(t)=C*sin(at)
Input(t) is a simple example of an analog IF signal, C is a constant and a varies from 35 MHz to 65 MHz                               I          ⁡                      (            t            )                          =                              Input            ⁡                          (              t              )                                *                      cos            ⁡                          (              bt              )                                                              =                  C          *                      sin            ⁡                          (              at              )                                ⁢                      cos            ⁡                          (              bt              )                                                              =                              (                          C              /              2                        )                    *                      [                                          sin                ⁢                                  {                                                            (                                              a                        +                        b                                            )                                        ⁢                    t                                    }                                            +                              sin                ⁢                                  {                                                            (                                              a                        -                        b                                            )                                        ⁢                    t                                    }                                                      ]                                                  =                              (                          C              /              2                        )                    *          sin          ⁢                      {                                          (                                  a                  -                  b                                )                            ⁢              t                        }                              
I(t) is the analog IF signal and b is 50 MHz. The term in sin(a+b)t is deleted by the low pass filter.                               Q          ⁡                      (            t            )                          =                              Input            ⁡                          (              t              )                                *                      sin            ⁡                          (              bt              )                                                              =                  C          *                      sin            ⁡                          (              at              )                                ⁢                      sin            ⁡                          (              bt              )                                                              =                              (                          C              /              2                        )                    *                      [                                          cos                ⁢                                  {                                                            (                                              a                        -                        b                                            )                                        ⁢                    t                                    }                                            +                              cos                ⁢                                  {                                                            (                                              a                        +                        b                                            )                                        ⁢                    t                                    }                                                      ]                                                  =                              (                          C              /              2                        )                    *          cos          ⁢                      {                                          (                                  a                  -                  b                                )                            ⁢              t                        }                              
Q(t) is the analog Q signal. The term in cos(a+b)t is deleted by the low pass filter.
As shown in the above equations, the LPFs pass the components having xe2x80x9ca-bxe2x80x9d which varies from xe2x88x9215 MHz to 15 MHz. This means that the frequencies of the output signals of the mixer 21 are from about 0 Hz to about 15 MHz. Therefore the cut-off frequencies of the LPFs 23 and 25 can be about 16 MHz. This reduces the demands of the higher sampling frequency of the ADC and the higher operation speeds of the following devices, such as the DSP 14 and the memory 16.
The use of the analog IQ splitter, however, introduces another problem, namely that it is difficult to keep the amplitude and the phase of the analog I and Q signals in balance. It comes from the difficulty of making the characteristics of the analog I and Q signal paths the same, especially the LPFs. This problem becomes worse when the bandwidth of the analog IF signal is wider. One of the factors is the group delay as shown in FIG. 4. In other words, the propagation speed of the signal in the signal path is different according to the frequency. Generally speaking, the propagation delay increases as frequency increases and the increase of delay with frequency is non-linear. Therefore the digital IQ splitter is better only from the viewpoint of keeping the amplitude and the phase of the I and Q signals in balance. Therefore what is desired is to provide a wide band IQ splitting apparatus suitable for splitting a wide band analog input signal into I and Q signals with balanced amplitude and phase between them. What is further desired is to provide a calibration method for the wide band IQ splitting apparatus.
The present invention provides a wide band IQ splitting apparatus for splitting an analog input signal into analog I (In-phase) and Q (Quadrature) signals while keeping the amplitude and the phase of the I and Q signals in balance. A quadrature oscillator generates a pair of quadrature signals. An amplitude and phase adjuster receives the quadrature signals and adjusts the balances of the amplitude and the phase between them. An analog splitter mixes an analog input signal with the pair of quadrature signals for splitting the analog input signal into analog I and Q signals. First and second analog to digital converters convert the analog I and Q signals into digital I and Q signals, respectively. A processor detects imbalance of the amplitude and phase between the digital I and Q signals and controls the amplitude and phase adjuster.
The amplitude and phase adjuster is previously calibrated. For this first calibration, the analog splitter receives a first calibration signal instead of the analog input signal. The first calibration signal has a known amplitude and a known frequency slightly different from the frequency of the quadrature signals. Then the processor detects imbalance of the amplitude and/or the phase between the digital I and Q signals for controlling the amplitude and phase adjuster properly. The frequency difference between the frequency of the first calibration signal and that of the quadrature signal is small enough that the group delay can be neglected and large enough that the processor can detect the frequency difference.
The processor according to the present invention produces compensation data in a second calibration. For the second calibration, the analog splitter receives a second calibration signal instead of the analog input signal. The frequency of the second calibration signal varies within the band of the analog input signal and the processor calculates compensation data at a plurality of frequencies of the calibration signal and a memory stores the compensation data. The frequency of the second calibration signal can vary step by step, or by a increment or a decrement. The amount by which the frequency changes in each step is small enough that the group delay can be neglected and large enough that the processor can detect the difference. The processor can calculate compensated frequency domain data from the digital I and Q data by using the compensation data and can calculate time domain data from the compensated frequency domain data.
The amplitude and phase adjuster can include a variable phase controller and a gain variable amplifier. The variable phase controller controls the phase of one of the quadrature signals. The gain variable amplifier controls the gain of one of the quadrature signals. The analog IQ splitter can have a mixer and a pair of low pass filters. The mixer mixes the analog input signal with the pair of quadrature signals. The low pass filters receive the output signals of the mixer and suitably limit the bandwidths of the analog I and Q signals. In this case, the frequency of the quadrature signals is approximately equal to the center frequency of the band of the analog input signal.